Thanks to Moore’s law, integrated circuit (IC) functionality as well as complexity have been increasied exponentially. This serves the even faster increasing demand of user requirements. However, such ICs become more and more difficult to design and to verify. While design tools and technologies for system-on-chip (SoC) and reusable Intellectual Property Components (IP cores) allow more complex hardware systems to be designed effectively, the verification methodologies are less effective. This leads to an enlarging productivity gap between design and verification such that verification can constitute about 70% of the total design effort. Therefore, there are increasing demands on effective verification flows that can help to reduce the verification cost. This paper proposes a novel formal verification methodology for digital hardware designs in System on Chips. This methodology has been applied to verify some industrial hardware designs. Several bugs in those systems have been detected
