In this paper, a new design of clock generator applied for high-speed and wide-band receiver is discussed. The circuit generates 4 local oscillators (LO) at frequency fLO = 0.5*fCLK from input clock frequency fCLK , which is in the range of 800 MHz – 12 GHz; and 8 phases Φ, by selecting 3 bits S0 S1 S2, at sampling frequency fS = 400 MHz—425 MHz. LO clocks and Φ phases are designed to satisfy the strict requirements such as falling/rising time, non-overlapping, pulse width and synchronization, power consumption (<20 mW). The proposed clock generator is implemented in CMOS 65nm and simulated in Cadence at TT/85 oC.
