A Low Area AES Encryption Core with Silicon Demonstration in 180nm CMOS Process ☆

This paper presents a low area, low power AES encryption core with the combination of several optimized components in the AES core and some modifications in the core architecture for emerging wireless networks and IoT systems. The detail results of area-speed-power trade-offs in the proposed AES core design are also presented and discussed. The implementation and chip measurement results in 180nm CMOS technology show that the proposed AES encryption core can reduce the area and power consumption significantly. The power consumption of the proposed AES encryption core is only 7.1 µW/MHz and the area is 2.3 Kgates which are much lower than other AES cores presented in literature.